WATLOWCLS200, MLS300, and CAS200 Communications Specification

with the 7th bit set—in other words, it sends an x41 or x48.

STS (The Status Byte)

• The controller uses the status byte, or STS, to return general status 

and error flags to the host software. (The controller ignores the status 

byte in the host software's command packet.) The next table shows 

status byte values and definitions. 

• An “x” in the status bytes below indicates that the associated nibble 

may contain additional information. In most cases, the status byte is 

composed of two independent nibbles. Each nibble is independent 

so that two codes can return at once. For example, status code F1 

indicates that data has changed (Fx) and the controller is being 

updated through the front panel (x1).

Status

in Hex Description

00 The controller has nothing to report, or AB protocol is selected.

01 Access denied for editing. The controller is being updated through the 

front panel.

02 AIM Comm failure.

A0 A controller reset occurred.

Cx The controller received a command that was not a block read or block 

write. (Command Error)

Dx The block write command attempted to write beyond a particular parameter block boundary, or the host software attempted to access a data table 

block that does not exist. (Data Boundary Error)

Ex The Alarm_Status variable has changed. The software should query the 

alarm status block to determine the particular alarm flag that changed.

Fx The controller altered shared data, either internally (from the firmware) or 

externally (from the keyboard). The host software should read the Data 

Changed Register to determine which data has been altered and update 

its own run-time memory

TNSL

• Least significant byte of the transaction number. This is the first half 

of a “message stamp.”

• The controller sends back the TNSL and TNSH exactly as it received 

them, so host software can use the TNSL and TNSH bytes to keep 

track of message packets.

TNSH 

• Most significant byte of the transaction number. This is the second 

half of the “message stamp.” 

ADDL

• The low byte of the beginning data table address of the block of data 

to read or write.

ADDH

• The high byte of the beginning data table address of the block of data 

to read or write.

DATA

• The new values to be set with a write command, or the requested data 

in a response to a read command.

DLE ETX

• Every packet of information must end with the codes DLE ETX. 

These codes signal the end of a transmission.

BCC or CRC

• Communications packets include a one- or two-byte error check at 

the end of the packet. There are two error check methods: Block 

Check Character (BCC), which requires 1 byte, and Cyclic Redundancy Check (CRC), which requires 2 bytes.

Watlow Anafaze recommends that you use the default error check

method, BCC. It is easier to implement than CRC, and it is acceptable

for most applications.

Select one error check method and configure both software and

controller for that method, or they will be unable to communicate.

The error check methods work this way:

Block Check Character (BCC)

BCC checks the accuracy of each message packet transmission. It

provides a medium level of security. The BCC is the 2’s complement of

the 8-bit sum (modulo-256 arithmetic sum) of the data bytes between

the DLE STX and the DLE ETX. (1’s complement +1)

• BCC does not detect transposed bytes in a packet. 

• BCC cannot detect inserted or deleted 0 values in a packet.

• If you have sent an x10 as data (by sending DLE x10) only one of the 

DLE data bytes is included in the BCC’s sum (the DLE = x10 also).

For instance, the block read example shown in the examples section, 

adds x08 00 01 00 00 80 02 10. Note that the x10 representing DLE 

has been left out of the calculation. The sum should come to x9B.

Cyclic Redundancy Check (CRC)

CRC is a more secure error check method than BCC. It provides a very

high level of data security. It can detect:

• All single-bit and double-bit errors.

• All errors of odd numbers of bits.

• All burst errors of 16 bits or less.

• 99.997% of 17-bit error bursts.

• 99.998% of 18-bit and larger error bursts.

The CRC is calculated using the value of the data bytes and the ETX

byte. At the start of each message packet, the transmitter must clear a

16-bit CRC register. 

When a byte is transmitted, it is exclusive-ORed with the right 8 bits of

the CRC register and the result is transferred to the right 8 bits of the

CRC register. The CRC register is then shifted right 8 times by inserting

0’s on the left. 

Each time a 1 is shifted out on the right, the CRC register is ExclusiveORed with the constant value xA001. After the ETX value is

transmitted, the CRC value is sent, least significant byte (LSB) first.

Below is a structured English procedure from AB Manual:

data_byte = all application layer data, ETX

CLEAR CRC_REGISTER

FOR each data_byte

GET data_byte

XOR (data_byte, right eight bits of CRC_REGISTER)

PLACE RESULT in right eight bits of CRC_REGISTER

DO 8 times

Shift bit right, shift in 0 at left

IF bit shifted =1

XOR (CONSTANT, CRC_REGISTER)

PLACE RESULT in CRC_REGISTER