EMERSONDeltaV SISTM Logic Solver

proof test automatically. A warning is given to the operator 

before the automatic proof test is started.

Sequence of Events Capability

With DeltaV SIS, events are automatically generated as 

function blocks are executed within a module scan. Events 

are time stamped with a resolution of <1 ms, and they are 

recorded in the sequence that they occur in the Event 

Chronicle. When using standard function blocks such as 

input blocks, voter blocks, and cause and effect blocks, a 

standard set of events are automatically generated without 

special configuration or programing required. For example, 

I/O failures, trip limits, first outs, and other similar events 

are automatically time stamped by function blocks and 

recorded in the Event Chronicle. When a process variable 

exceeds the trip limit, DeltaV SIS records the event along 

with the analog value and the trip condition.

In general, when there is a plant event that triggers an 

emergency shutdown from the SIS, one input will exceed 

a trip limit on one scan and this will cause outputs to trip 

and more inputs will then change state. Sequence of 

Events Recording has been used to find that first input that 

caused the trip by looking at all of the inputs in the plant. 

With the DeltaV SIS system, the operator simply filters the 

Event Chronicle for first out trips, and the first-out is clearly 

visible. 

If higher resolution is required for some channels then 

they can be wired to both the DeltaV SIS Logic Solver and 

also to a DeltaV Discrete Input Card for Sequence of 

Events, which provides a resolution of 0.25 ms.

DeltaV SIS Product Data Sheet

May 2013 – Page 6 DeltaV SIS Logic Solver

System Compatibility

DeltaV SLS 1508 Specifications

SLS 1508 Logic Solver Weight, Heat Generation and Power Consumption

Item Specifications:

Redundant Logic Solver

Weight – 1.20 kg

Heat Dissipation – 24 W

Power – 2 A @ 24 V DC + Dig out Field Loads

DeltaV SIS Product Data Sheet

May 2013 – Page 8 DeltaV SIS Logic Solver

Channel Specifications

The Logic Solver provides 16 channels of flexible I/O, meaning that each channel can be configured as an Analog Input 

(HART), HART Two-State Output, Discrete Input, or Discrete Output channel. 

Analog Input Channel Specifications (includes HART)

Item Specifications:

Number of channels 16

Isolation

Each channel is optically isolated from the system 

and factory-tested to 1500 V DC. No channel-tochannel isolation.

Nominal signal span 4 to 20 mA

Full signal range 1 to 24 mA

2-wire transmitter power 15.0 V minimum terminal-to-terminal @ 20 mA; 

current limited to 24 mA max

Safety / diagnostic accuracy 2.0% of span

Resolution 16 bits

Filtering

2-pole, corner frequency 5.68 Hz

-3 dB at 5.68 Hz

-20.0 dB at 40 Hz (half the sample rate)